Last updated on September 18, 2026
Based on MPU, we can build a total hierarchy architecture for MPC system: from MPU, to MPU system on one motherboard, to MPC cluster.
Herein, CPU can be CGPU which combines CPU and GPU. MPC is Memory Parallel Computing. MPU is Memory Parallel processing Unit.
MPU sound much better and consistent with CPU/GPU, so I change all names including PCMem be based on MPU, and MPU = MPU processor + MPU memory.
One MPC cluster in MPC total architecture can be formed by 2 following layers:
layer-1) MPU system: MPU to CPU on one MPU motherboard
Structure: MPU memory unit of each MPU – <MPU internal bus> – MPU processor of the MPU – <MPU external bus> – MPU chip – <MPU PCB bus> – MPU PCB I/O – <MPU motherboard bus> – MPU controllor – CPU or GPU or CGPU.
A MPU bus forms a single broadcast domain – a MPU domain, and an MPU domain includes CPU, GPU, and MPUs which all share the same broadcasting on the bus.
The MPU controller on a MPU motherboard bus can be separated from or integrated in CPU or GPU or CGPU.
It can be designed as that DRAM connects to CPU in a MPU domain through a separated motherboard bus not the MPU motherboard bus, and it can also be designed as that DRAM connects to CPU in a MPC domain through the MPC motherboard bus.
One MPU domain includes only one MPU motherboard bus and at least one CPU (CGPU).
Multiple MPU domains (including buses and CPUs) can be integerated on one MPU motherboard with a shared DRAM through a separated DRAM bus.
Multiple MPU domains on one MPU motherboard can form one broadcast domain by connecting their motherboard buses.
A universal reduction tree on one MPC motherboard can span from inside each MPU to all MPC domains on the motherboard.
layer-2) From motherboard to MPC cluster
Multiple MPU domains on different motherboards can connect together by outside link/server/switch to form a MPC cluster, and this MPC cluster forms one broadcast domain combined by the multiple MPU domains.
The MPC cluster could have a reduction tree for sum & max, which extends the universal reduction tree in each MPU motherboard, in each MPU domain, in and outside each MPU. (PS: by the way, reduction tree is separated and independent from bus, you guys know this basics, right? )
The different MPU domains in one MPC cluster can do parallel read/write to improve the read/write speed of MPU and MPU memories.
MPC cluster can be flexible and dynamic for all MPU domains connected together to be one MPC cluster or multiple parallel MPC clusters or even a hierarchy of multiple tiers of MPC clusters, which can adapt to requirements for different models, tasks, context sizes and broadcast domains.
Through MPC cluster, more MPU sticks on separated motherboards can work together to contain larger memory space for longer context with higher read/write speed of MPUs.
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